Reliability-aware memory design using advanced reconfiguration mechanisms

Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens.Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suced

Statistical lifetime analysis of memristive crossbar matrix

Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.Postprint (published version

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Resistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.Peer ReviewedPostprint (author's final draft

A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm

High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized and implemented on an FPGA and as an ASIC. The results of such implementations are compared with metrics such as performance and area. The performance in the parabolic architecture is shown to exceed the CORDIC architecture by a factor 4.2, in a 65 nm Standard-VT ASIC implementation

Reliability challenges in design of memristive memories

Postprint (author’s final draft

The non-linear properties of random water waves and associated particle kinematics

SIGLELD:D45576/83 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Proactive reconfiguration, a methodology for extending SRAM lifetime

The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique and furthermore it takes into account the process variability impact on the memory components. Our results show between a 30% and a 45% of system lifetime increase over the existing proactive reconfiguration technique and 1.7X to ~10X improvement to non-proactive reconfiguration one

Lepton flavour violation, Yukawa unification and neutrino masses in supersymmetric unified models

We explore some phenomenological consequences of models based on supersymmetric extensions of the Standard Model. In particular, we focus on the Minimal Supersymmetric Standard Model supplemented by right-handed neutrinos in the context of the Pati-Salam SU(4) x SU(2)_L x SU(2)_R Grand Unified Theory. We start by analysing the possibility of using Lepton Flavour Violation as a probe of physics beyond the Standard Model. We show that the #mu# #-># e#gamma# and #tau# #-># #mu##gamma# decays impose important constraints to the soft supersymmetry breaking parameters of the Pati-Salam model that already allow the formulation of lower bounds for the masses of the lighter supersymmetric particles. Secondly, we investigate how third family Yukawa unification can be used to provide a window into the soft supersymmetry breaking Lagrangian. We show that, a successful top quark mass prediction requires that the supersymmetric corrections to the bottom quark mass are small which, in turn, imposes a distinct hierarchy between the soft breaking parameters. Finally, we explicitly construct a realistic model of quark, charged lepton and neutrino masses and mixing angles, based on the Pati-Salam. gauge group supplemented by an abelian flavour symmetry, that can explain the large atmospheric neutrino mixing angle, suggested by the Super-Kamiokande data, and account for the large mixing angle Mikheyev-Smirnov-Wolfenstein solution to the solar neutrino problem. (author)Available from British Library Document Supply Centre-DSC:DXN040592 / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Proactive reconfiguration, a methodology for extending SRAM lifetime

The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique and furthermore it takes into account the process variability impact on the memory components. Our results show between a 30% and a 45% of system lifetime increase over the existing proactive reconfiguration technique and 1.7X to ~10X improvement to non-proactive reconfiguration one.Postprint (published version